Synthesis Report Synopsys Lattice Technology Mapper, Version maplat201209latp1, Build 002R, Built Dec 20 2012 01:51:42 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF666 |Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) @N:"c:\develop\hwdesign\lattice\projects\machxo2\led_blinkers\triple_led.vhd":19:4:19:5|Found counter in view:work.tled(tled_arch) inst counter[25:0] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) @N: FX164 |The option to pack flops in the IOB has not been specified Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 26 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================================================== Non-Gated/Non-Generated Clocks ============================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------------------------------------------- @K:"@|S:clk@|E:counter[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001" clk port 26 counter[0] ======================================================================================================================================================= ===== Gated/Generated Clocks ===== ************** None ************** ---------------------------------- ================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\Develop\HwDesign\Lattice\projects\MachXO2\LED_blinkers\triple_led\triple_led_triple_led.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Writing EDIF Netlist and constraint files G-2012.09L-1 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 78MB) @W: MT420 |Found inferred clock tled|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Jun 25 17:54:12 2013 # Top view: tled Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 994.116 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------- tled|clk 1.0 MHz 169.9 MHz 1000.000 5.885 994.116 inferred Inferred_clkgroup_0 ======================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------ tled|clk tled|clk | 1000.000 994.116 | No paths - | No paths - | No paths - ============================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: tled|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------- counter[0] tled|clk FD1S3AX Q counter[0] 0.972 994.116 counter[1] tled|clk FD1S3AX Q counter[1] 0.972 994.258 counter[2] tled|clk FD1S3AX Q counter[2] 0.972 994.258 counter[3] tled|clk FD1S3AX Q counter[3] 0.972 994.401 counter[4] tled|clk FD1S3AX Q counter[4] 0.972 994.401 counter[5] tled|clk FD1S3AX Q counter[5] 0.972 994.544 counter[6] tled|clk FD1S3AX Q counter[6] 0.972 994.544 counter[7] tled|clk FD1S3AX Q counter[7] 0.972 994.687 counter[8] tled|clk FD1S3AX Q counter[8] 0.972 994.687 counter[9] tled|clk FD1S3AX Q counter[9] 0.972 994.830 =================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- counter[25] tled|clk FD1S3AX D counter_s[25] 999.894 994.116 counter[23] tled|clk FD1S3AX D counter_s[23] 999.894 994.258 counter[24] tled|clk FD1S3AX D counter_s[24] 999.894 994.258 counter[21] tled|clk FD1S3AX D counter_s[21] 999.894 994.401 counter[22] tled|clk FD1S3AX D counter_s[22] 999.894 994.401 counter[19] tled|clk FD1S3AX D counter_s[19] 999.894 994.544 counter[20] tled|clk FD1S3AX D counter_s[20] 999.894 994.544 counter[17] tled|clk FD1S3AX D counter_s[17] 999.894 994.687 counter[18] tled|clk FD1S3AX D counter_s[18] 999.894 994.687 counter[15] tled|clk FD1S3AX D counter_s[15] 999.894 994.830 ======================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.894 - Propagation time: 5.779 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 994.116 Number of logic level(s): 14 Starting point: counter[0] / Q Ending point: counter[25] / D The start point is clocked by tled|clk [rising] on pin CK The end point is clocked by tled|clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------- counter[0] FD1S3AX Q Out 0.972 0.972 - counter[0] Net - - - - 1 counter_cry_0[0] CCU2D A1 In 0.000 0.972 - counter_cry_0[0] CCU2D COUT Out 1.545 2.516 - counter_cry[0] Net - - - - 1 counter_cry_0[1] CCU2D CIN In 0.000 2.516 - counter_cry_0[1] CCU2D COUT Out 0.143 2.659 - counter_cry[2] Net - - - - 1 counter_cry_0[3] CCU2D CIN In 0.000 2.659 - counter_cry_0[3] CCU2D COUT Out 0.143 2.802 - counter_cry[4] Net - - - - 1 counter_cry_0[5] CCU2D CIN In 0.000 2.802 - counter_cry_0[5] CCU2D COUT Out 0.143 2.945 - counter_cry[6] Net - - - - 1 counter_cry_0[7] CCU2D CIN In 0.000 2.945 - counter_cry_0[7] CCU2D COUT Out 0.143 3.087 - counter_cry[8] Net - - - - 1 counter_cry_0[9] CCU2D CIN In 0.000 3.087 - counter_cry_0[9] CCU2D COUT Out 0.143 3.230 - counter_cry[10] Net - - - - 1 counter_cry_0[11] CCU2D CIN In 0.000 3.230 - counter_cry_0[11] CCU2D COUT Out 0.143 3.373 - counter_cry[12] Net - - - - 1 counter_cry_0[13] CCU2D CIN In 0.000 3.373 - counter_cry_0[13] CCU2D COUT Out 0.143 3.516 - counter_cry[14] Net - - - - 1 counter_cry_0[15] CCU2D CIN In 0.000 3.516 - counter_cry_0[15] CCU2D COUT Out 0.143 3.659 - counter_cry[16] Net - - - - 1 counter_cry_0[17] CCU2D CIN In 0.000 3.659 - counter_cry_0[17] CCU2D COUT Out 0.143 3.801 - counter_cry[18] Net - - - - 1 counter_cry_0[19] CCU2D CIN In 0.000 3.801 - counter_cry_0[19] CCU2D COUT Out 0.143 3.944 - counter_cry[20] Net - - - - 1 counter_cry_0[21] CCU2D CIN In 0.000 3.944 - counter_cry_0[21] CCU2D COUT Out 0.143 4.087 - counter_cry[22] Net - - - - 1 counter_cry_0[23] CCU2D CIN In 0.000 4.087 - counter_cry_0[23] CCU2D COUT Out 0.143 4.230 - counter_cry[24] Net - - - - 1 counter_s_0[25] CCU2D CIN In 0.000 4.230 - counter_s_0[25] CCU2D S0 Out 1.549 5.779 - counter_s[25] Net - - - - 1 counter[25] FD1S3AX D In 0.000 5.779 - =================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2_1200hc-4 Register bits: 26 of 1280 (2%) PIC Latch: 0 I/O cells: 4 Details: CCU2D: 14 FD1S3AX: 26 GSR: 1 IB: 1 OB: 3 PUR: 1 VHI: 1 VLO: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 24MB peak: 78MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Jun 25 17:54:12 2013 ###########################################################]